Level shift circuits are necessary in digital circuits that belong to high-speed, differential logic families such as emitter coupled logic (ECL) or current mode logic (CML). These circuits provide a wideband solution for obtaining a full diode voltage (Vbe) drop in the common-mode direct current (DC) voltage level of alternating current (AC) input signals. A typical circuit that requires such a level shift circuit is an ECL latch such as that shown in prior art FIG. 1A. The ECL latch requires a differential AC clock input signals (CLK, CLKX) whose common-mode DC voltage must be shifted down from the common-mode DC voltage of the differential data input signals (D, DX) for proper circuit operation to occur. In particular, for the representative ECL latch shown in FIG. 1A, the base to collector junctions of devices connected to the clock inputs CLK and CLKX would be forward biased if the common-mode DC level of the differential clock input signals were not shifted down from the common-mode DC level of the data inputs D and DX. Thus, it becomes necessary to lower the common-mode DC level of the clock input signals CLK and CLKX to a low enough potential to avoid forward biasing the base to collector junctions of the current steering transistors. A variation of the problem where three bias levels are required is shown in FIG. 1B.
One typical circuit which has been extensively used to lower the common-mode DC level of an AC signal is the emitter follower circuit shown in prior art FIG. 2. This type of circuit has been developed to lower the common-mode DC voltage level of the clock input signals by an amount equal to a full base to emitter voltage drop for a given bias current. Since the common-mode DC level of the incoming clock signals at terminals INO and INOX is approximately at the supply voltage, the emitter follower circuit lowers the common-mode DC level of the clock signals at terminals Q1 and Q1X by a full diode drop below the supply voltage. By keeping the input resistance to the level shifting circuit low, the bandwidth of the input signal may be kept relatively constant.
An alternative configuration for obtaining a full diode drop level shift without limiting the input signal's AC bandwidth is shown in prior art FIG. 4. This approach uses the path through a high-speed differential buffer to maintain high output signal bandwidth. In this approach, a diode connected bipolar transistor is used to drop the differential buffer's supply voltage by a fill diode drop or by about 0.9 volts. Thus, the common-mode DC level of the output signals appearing at terminals CLK.sub.-- OUT and CLK.sub.-- OUTX is shifted down by a full diode drop from the input signals.
The problem with the full diode drop level shift circuits identified in FIG. 2 and FIG. 4 is that the present design environment for integrated circuits requires circuit operation in the presence of supply voltages as low as 1.8 volts DC for circuits with two DC bias levels such as the latch in FIG. 1A. A similar requirement is for circuits with three bias levels (such as the circuit in FIG. 1B) to operate at 2.7 volts. In a contemporary, small-geometry bipolar process, a base to emitter diode voltage drop is approximately 0.9 volts for active devices that are biased for high speed operation. When the supply voltage is lowered to 1.8 volts and the common-mode DC level of the clock input signals is shifted down by 0.9 volts through the use of the full diode drop level shift circuits illustrated in FIG. 2 or FIG. 4, the resulting common-mode DC level of the signals appearing at terminals CLK and CLKX of FIG. 1A is 0.9 volts below the 1.8 volt supply voltage, i.e. 0.9 volts. Again, since a base to emitter voltage drop is around 0.9 volts, the DC voltage level present at the emitters of devices Q2 and Q3 in FIG. 1A will be approximately zero volts.
Thus, the collector to emitter voltage of the current sinking transistor, Q1 in FIG. 1A, will also be approximately zero volts. In the presence of the required bias voltage of around 0.9 volts at the base of transistor Q1, the base to collector voltage of Q1 would be sufficiently high to forward bias this junction, and Q1 would be in saturation and would not act as a current sink. Therefore, it is not possible to operate digital circuits that belong to high-speed, differential logic families such as emitter coupled logic (ECL) or current mode logic (CML) with traditional full diode drop level shift circuits when operating with supply voltages as low as 1.8 volts. These circuits provide a wideband solution for coupling the outputs of CML logic circuits with the inputs to other logic circuits that require a different DC potential without changing the logic information present at the transmitting circuit output. Thus, the circuit in FIG. 1A illustrates the role of the level shift circuit in CML logic.
FIG. 1A can be treated as a transmitting circuit consisting of a pair of resistors R1 and R2 with equal value resistance. One terminal of each resistor is connected to a supply voltage (Vdd). The remaining terminals OUT and OUTX of the resistors are driven by a pair of linked bi-value currents I1 and I2. When I1 is at value I, I2 is at value 0. Conversely, if I2 is at value I, I1 is at value 0. In this way, a logic signal is defined between terminals OUT and OUTX of the circuit. Logic HIGH is defined when the voltage at terminal OUT is approximately equal to Vdd while the voltage at OUTX is approximately equal to Vdd-Vlogic, where Vlogic is the product of resistor value R and current value I. Logic LOW is defined when the voltage at terminal OUTX is approximately equal to Vdd while the voltage at OUT is approximately equal to Vdd-Vlogic. Typically Vlogic is defined with value sufficiently large to steer substantially all the current in a bipolar diffamp to one collector of the amplifier but small compared to a silicon diode voltage. A typical value is 150 millivolts (mV).
In FIG. 1B is a typical receiving circuit illustrating logic with three DC bias levels. The circuit consists of differential amplifiers (devices Q11 through Q16) stacked to form an AND gate. The output voltage is generated by drawing current through differential load resistors R3 and R4. The circuit is biased by source Q7 with fixed value I. Logic levels at the output are defined in the same manner as in the transmitting circuit. As seen in the figure, output terminal AND is at logic HIGH only when terminal A is at high potential compared to AX, B is at high potential compared to BX and C is at high potential compared to CX.
The need for level shifting the inputs to the receiving circuit is demonstrated by studying the DC voltage constraints at the inputs to the receiving circuit. If the transmitting circuit is coupled to terminals A and AX, acceptable performance can be achieved. If it is assumed that terminals A and AX are excited by a voltage between Vdd and Vdd-Vlogic, application of similar voltages to terminals B and BX results in saturation of devices Q13 and Q14. This results in slow or incorrect circuit operation. Clearly, the DC level of the voltages applied to terminals B and BX must be shifted down with respect to the voltages applied at A and AX by at least Vsat, the minimum voltage applied across a bipolar collector-emitter junction to keep that device from saturating. Similarly, the voltages at terminals C and CX must be below the voltages at B and BX by at least Vsat. At the same time, the logic definitions of the signals must be preserved. For these operations a level-shift circuit is needed.
As discussed above, the problem with the full diode drop level shift circuits identified in FIG. 2 and FIG. 4 is that the present design environment for integrated circuits requires supply voltages to be minimized. In a contemporary, small-geometry bipolar process, a base to emitter diode voltage drop is approximately 0.9 volts for active devices at room temperature that are biased for high speed operation. Using full diodes for level-shifts and assuming a Vsat of 0.4 volts, the minimum voltage Vdd applied required for correct circuit operation in FIG. 1B is 3.1 volts at room temperature. For a circuit with only two inputs (FIG. 1A) a supply voltage of 2.2 volts is required. To meet industry supply voltage standards, it is desirable to operate at voltages as low as 2.7 volts with 3 levels of logic and 1.8 volts with 2 levels of logic.
A solution to this problem is to create a level-shift circuit that produces a DC level shift that is a fraction of a diode drop. In that way, three-level logic could be supported by coupling an CML transmitting signal (FIG. 1A) directly to the A inputs of a receiver, through the fractional diode level shifter to the B inputs of the receiver and though a full-diode level shifter to the C inputs of the receiver. For two-level logic, only the A and B connections would be required.
A fractional-diode level-shift circuit would behave optimally if the level-shift voltage is set to 1/2 Vbe and maintained at that value over all operating temperatures. This can be seen by returning again to the receiving circuit in FIG. 1B. Assume that input pairs A, B and C are driven by 0, F and 1 diode level shifts, respectively, where F is a fraction between 0 and 1. If F is greater than 0.5, this moves transistors Q15 and Q16 closer to or into saturation. If F is less than 0.5, this moves transistors Q13 and Q14 closer to or into saturation. Maximum immunity to device saturation on both Q13, Q14 and Q15, Q16 is achieved when F is at 0.5. Since diode voltage Vbe is a function of temperature, the level shift voltage (F)(Vbe) should track in proportion to Vbe with temperature for optimal performance.
One way to avoid having to lower the clock input signal's common-mode DC voltage by the full 0.9 volt diode drop is shown in prior art FIG. 3. This circuit uses R1 and R2 to lower the common-mode DC level of the input signal by an arbitrary fraction of a base to emitter voltage drop. Resistors R1 and R2 form a voltage divider which sub-divides the voltage between the base and emitter of Q1'. Since the circuit produces a voltage drop that is some fraction of a full base to emitter voltage drop, it is referred to herein as a sub-Vbe level shifting circuit. When a 1.8 volt supply is used, dropping the voltage by less than 0.9 volts allows the latch in FIG. 1 to operate correctly. Annotated in FIG. 1A are DC bias voltages that would allow proper high-speed operation of this example ECL or CML latch. These DC bias voltages indicate that a half-diode drop level shift of 0.45 volts would allow proper circuit operation.
An inherent problem with the sub-Vbe circuit illustrated in FIG. 3 is a significant reduction in circuit speed and bandwidth due to the presence of a large time constant directly in the signal path. This occurs because resisters R1 and R2 must be made large enough not to sink substantial current from previous stages. This large resistance, together with the input capacitance of the level shifting transistors, forms a long time constant relative to the period of the incoming signals. An example of this scenario might be a contemporary IC process for which a minimum-sized NPN transistor's base transit time is 9.9 pS and for which the maximum transition frequency (F.sub.t) has been found to occur at a collector bias current of 200 uA. In this situation and referring to FIG. 3, the base charging capacitance of Q1' would be approximately 75 fF and would dominate the maximum useful frequency of the device. Assuming that only 20 uA is to flow through R1 and R2 from the previous stage, then the values selected for R1 and R2 each will be about 33 K Ohms. With this value of resistance attached to the base terminal, the corner frequency would be only approximately 32 Mhz at the input of the sub-Vbe level shift circuit. This frequency response is not adequate for the present high frequency design environment around 3-4 GHz.
Therefore, the need exists for a circuit configuration for application as a DC level offset for wideband AC signals. The circuit should be applicable to future generations of land-mobile and cellular radios and capable of operating within a frequency range of up to 3-4 GHz with all components integrated on a single IC substrate. Traditional full diode drop level shifting circuits do not work with ECL and CML logic structures at low supply voltages. Thus, it would be desirable to have a circuit which would provide a fraction of a diode voltage drop DC voltage offset from a supply voltage or potential without limiting the bandwidth of the wideband signals. It would be further desirable if the fraction of a diode voltage drop could be maintained as a constant proportion of a diode voltage versus changes in temperature.